Cryoelectronics for Scalable Ion-Trap Quantum Control
Speaker
Farah Fahim
Division Director, Microelectronics Division, Fermi National Accelerator Laboratory, USA
Title
"Cryoelectronics for Scalable Ion-Trap Quantum Control"
Abstract
Realizing large-scale trapped-ion quantum information processing requires precise, low-noise, and energy-efficient control electronics that can be positioned close to the qubits without exceeding the cryogenic thermal budget. Conventional room-temperature control architectures rely on extensive cabling and external waveform generators, which introduce latency, noise pickup, and significant scalability limitations. This keynote presents a five-year effort to develop cryogenic, low-power, high-voltage ion-trap control electronics integrated directly at the 4 K stage, enabling a modular and scalable platform for next-generation trapped-ion quantum processors. The stringent electrical requirements for ion shuttling, splitting, potential shaping, and multi-zone control—including noise below 100 nV/√Hz, power consumption under 5 mW per channel, ±5–10 V waveform swings, 1–100 MHz update rates, and millivolt-level resolution while driving capacitive electrode loads—are shown to be achievable using commercial CMOS technologies when paired with rigorous cryogenic device characterization.
Comprehensive low-temperature studies of 22 nm FDX BOXFETs and GlobalFoundries 28 nm high-voltage devices (8 V and 25 V LDMOS) reveal predictable cryogenic trends such as threshold voltage shifts, substrate freeze-out, modified DIBL behavior, enhanced impact ionization, and self-heating effects, all of which can be accurately modeled and engineered around. Leveraging this device-level understanding, we developed the Cryogenic Ion-Trap Controller (CITC) ASIC family—CITC1, CITC2, and CITC3—based on a custom charge-based DAC architecture optimized for cryogenic waveform synthesis. The design integrates low-power on-chip SRAM, multi-stage level shifters from 1 V logic to 8–25 V domains, cascoded current-cell arrays for precision linear charging and discharging, and integrated 800 pF trench capacitors co-located with the trap electrodes. CITC3 demonstrates ±12 V arbitrary waveform generation at 1.25 MHz update rates with stable low-noise operation at 15 K. Integrated system testing at MIT Lincoln Laboratory successfully replaced room-temperature control channels with cryogenic CITC channels, enabling ion shuttling, swapping, and motional-heating-based noise characterization directly from cryogenic electronics. The talk concludes with a roadmap toward full cryogenic electrode control, cryogenic SPAD-based readout integration, and architectural enhancements for long-duration DC hold and active feedback, illustrating how co-designed cryoelectronics and ion-trap architectures enable scalable, high-fidelity quantum computing using commercial CMOS platforms.
Speaker Bio
Farah Fahim is the Microelectronics Division Director in the emerging technologies directorate at Fermi National Accelerator Laboratory. She is also a principal engineer specializing in mixed signal chip design. For over 20 years Farah has been developing low noise, high-speed readout and control electronics for detectors which operate in harsh environments such as high ionizing radiation and/or deep cryogenic temperatures for a wide range of applications. Her current research pursuits include on-chip artificial intelligence for data processing at source and designing ultra-low power, compact readout electronics for modular scalable cryogenic quantum systems.
She is an adjunct professor at Northwestern University and a Senior Scientist at University of Chicago. Farah has a Ph.D. in Electrical Engineering from Northwestern University.
Before joining Fermilab in 2009, Farah worked at the Rutherford Appleton Laboratory, UK. She received the best presenter award at IEEE Nuclear Science Symposium in 2016. She is a recipient of the DOE Early career research award.