Events

Hardware Realization and Implementation Security Evaluation of HQC, A NIST PQC Standard

Electrical and Computer Engineering
Lecture / Panel
 
For NYU Community
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Speaker

Sanjay Deshpande
Postdoctoral Scholar at Northwestern University

Title

"Hardware Realization and Implementation Security Evaluation of HQC, A NIST PQC Standard"

Abstract

Quantum computing is no longer a distant dream, its rapid progress is poised to revolutionize various fields from drug discovery to optimization. But this leap forward comes with a critical caveat: the pre-quantum public-key cryptographic algorithms that secure our digital infrastructure today such as RSA and ECC are at risk of being broken. With the rise of quantum capabilities, everything from encryption keys to biometric data could become vulnerable to adversaries.

The race is on to transition to quantum-safe cryptography before quantum computers reach a critical threshold. At the heart of this global effort lies Post-Quantum Cryptography (PQC), the new generation of cryptographic algorithms believed to be both quantum and classically secure. Organizations like NIST are leading international efforts to standardize these algorithms.

This talk explores the challenges and innovations in transitioning to PQC, with a special focus on the role of hardware implementation and evaluation in ensuring both performance and security. It will take a deep dive into the Hamming Quasi-Cyclic (HQC) algorithm, one of the candidates selected for standardization by NIST in 2025, and examine how HQC performs under practical constraints and potential side-channel threats.

About Speaker

Sanjay Deshpande is a Postdoctoral Scholar at Northwestern University, specializing in efficient and secure hardware implementations of post-quantum cryptography (PQC) and the security of quantum computing systems. He earned his Ph.D. in Electrical Engineering from Yale University, where his research advanced hardware architectures for PQC and quantum computer security.

Sanjay has over seven years of experience in FPGA/ASIC design, side-channel attack countermeasures, and hardware IP development, with industry research experience at Microsoft Research, SandboxAQ, and Technology Innovation Institute. He has published extensively in top venues (CHES, SAC, HOST, ACM TECS) and received multiple awards, including the Best of IEEE CAL Award (2023) and the Best Project Award at the Cyber-Physical Systems Summer School (2023).

In addition, he actively contributes to the research community as a reviewer and program committee member for leading conferences and journals in cryptography, hardware security, and quantum security.

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