NYU Processor Design (GY)
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Taking chips from conception to tape-out using cutting-edge technologies in open hardware design
The Processor Design team seeks to take novel microprocessor designs from ideation, through logic design, verification, synthesis, layout, and finally tape-out and validation in real silicon. In doing so the team hopes to develop student and institutional expertise in the tools and processes involved in the growing space of open-source hardware design.
Applicants should have completed CS-UY 2214 (Computer Architecture) or ECE-UY 2204 (Digital Logic and State Machine Design) or have equivalent experience with RTL design. Team participation assumes familiarity with Verilog and associated tooling.
Research, Design, and Technical Topics
- Register Transfer Level (RTL) design of modular microprocessor components
- Continuous integration pipeline for verification tests of RTL components
- Package management of RTL and other IP components for integration into final microprocessor designs
- Exploration of “No-Human-In-The-Loop” RTL-to-GDS synthesis
- Pre-silicon validation using FPGA synthesis targets
Methods and Technology
- C/C++ (Programming Language)
- Verilog/System Verilog (Hardware Description Language)
- Verilator (Verilog Simulator)
- YoSys (RTL Synthesis Framework)
- Git
Majors/Areas of Interest
- Computer Science
- Computer Engineering
- Electrical Engineering
Partners
- NYU Tandon School of Engineering
- Purdue University System-On-Chip Enhancement Technologies Team
Primary Instructors
