The Next Leap in Hardware Systems: Powered by Heterogenous Memory, Logic, and 3D Integration

Lecture / Panel
For NYU Community



Robert M. Radway
PhD Candidate, Department of Electrical Engineering, Stanford University


"The Next Leap in Hardware Systems: Powered by Heterogenous Memory, Logic, and 3D Integration"


Computing is at a critical juncture. Applications such as AI/ML demand much larger memory, higher bandwidth, and lower-energy compute compared to business as usual. New hardware systems, powered by heterogenous memory, logic, and 3D integration, are required for large energy efficiency, throughput, and scaleup benefits. I will present my contributions to three such heterogeneous systems:
1. The first edge AI/ML chips with full on-chip inference and training of CNNs and Transformers using foundry Resistive RAM (RRAM). The heterogeneous combination of RRAM and SRAM enables new circuit-architecture-algorithm interplay, resulting in 9× or higher end-to-end Energy- Delay-Product (EDP) benefits versus traditional duty-cycled systems using SRAM, DRAM, or Flash.
2. New multi-chip Illusion systems for scaleup to 16× larger AI/ML models with 11× or higher EDP benefits versus traditional systems. Illusion minimizes inter-chip traffic by co-optimizing per- chip memory size, heterogeneous inter- and intra-chip interconnects, and idle power via fine-grained power management, thus creating the illusion (within 10% EDP) of a Dream Chip with all resources on-chip.
3. The first foundry heterogeneous monolithic 3D hardware integrating silicon CMOS, carbon nanotube field-effect transistors and RRAM, demonstrating 4× memory bandwidth versus iso- footprint, apples-to-apples conventional designs. Such benefits are only possible through new 3D architectures instead of 3D physical design alone. Bigger benefits can be obtained for a wide set of applications by such hardware systems powered by a wider set of heterogeneous technologies. These also create exciting avenues for new courses.

About Speaker

Robert M. Radway is a Ph.D. Candidate in Electrical Engineering at Stanford University advised by Prof. Subhasish Mitra. He received his M.Eng. and B.S. in Electrical Engineering and Computer Science from MIT. His research focuses on building hardware systems leveraging heterogeneous memory, logic, and 3D integration for large benefits. His research contributions include the first published non-volatile Resistive RAM (RRAM) end-to-end systems hardware, the first edge AI/ML chips using foundry RRAM for full on-chip inference and training, multi-chip systems to efficiently scaleup to larger models, and the first foundry monolithic 3D hardware delivering large benefits. His honors include the Stanford Graduate Fellowship, the Symposium on VLSI Circuits Best Student Paper Award (2021), and the Symposium on VLSI Technology Best Student Paper Award (2023).