From Bits to Beyond: Crafting Secure and Scalable Memory Architectures for Next-Generation Systems

Lecture / Panel
For NYU Community

Prashant Nair standing in front of a painting


Prashant Nair
The University of British Columbia, Vancouver Campus


"From Bits to Beyond: Crafting Secure and Scalable Memory Architectures for Next-Generation Systems"


Modern memory systems face scalability, security, and efficiency challenges as applications demand more from them. DRAM cells, the building blocks of memory systems, suffer from reliability issues that expose new attack vectors. One such attack is Row Hammer, which allows adversaries to flip the contents of DRAM cells by repeatedly accessing them. This compromises the security and scalability of memory systems. Moreover, different computing hardware, such as GPUs and CPUs, have different memory capacities, which affects the efficiency of memory systems. 

This talk motivates the need for scalable, secure, and efficient memory systems. My presentation will dive deep into our latest HPCA 2023 paper (best paper) and discuss a novel attack called Juggernaut. Juggernaut breaks the state-of-the-art Row Hammer mitigation. My talk will discuss developing scalable and efficient solutions to mitigate Row Hammer. Going beyond security, I will briefly discuss our system-level proposal for enabling scalable memory systems (VLDB 2022) for large-scale ML models. I will conclude the talk by describing how research vectors in my research group, namely Quantum Computing, AI/ML memory system architectures, and security, are critical for developing next-generation systems.

About Speaker

Prashant Nair is an Assistant Professor at the University of British Columbia (UBC). He is also an Affiliate Fellow at the Quantum Algorithms Institute. His primary interests are Computer Architecture, Quantum Systems, AI/ML Systems, Memory Systems, Reliability, and Security. He leads the "Systems and Architectures (STAR) Lab."

Dr. Nair has published over 25 papers in top-tier venues such as ISCA, MICRO, HPCA, ASPLOS, DSN, SC, and VLDB. He has received several awards, including the best paper award at HPCA 2023, two honourable mentions for IEEE MICRO Top-Picks, and the ECE Graduate Research Assistant Excellence Award for his Ph.D. at Georgia Tech. Before joining UBC, he worked at the T. J. Watson Research Center, developing practical data compression techniques for IBM systems. His work on integrating On-Die ECC and Host ECC (XED @ ISCA-2016) has been adopted by the HBM3 Memory Protocol by JEDEC.