Jan Moritz Joseph
RWTH Aachen University
"Architectures, Compilers, and Hardware Security for Neuromorphic Computing-in-Memory Systems"
Recently, memory technologies emerged that enable data storage and computation within the same hardware block. This Computing-In-Memory (CIM) technology enables fundamentally novel architectures not limited by data movements. There are different technology contenders, e.g., Resistive Random Access Memory (RRAM) that can be used for efficient matrix-vector multiplications in memory, accelerating the dominant operations in ML inference and training. Therefore, CIM technology is one cornerstone of novel computing concepts to achieve more efficient and pervasive AI, disrupting its application and bringing complex models to the end user. This talk will summarize the current state-of-the-art for CIM edge-AI accelerators to motivate their key advantage. We will also discuss this technology's challenges before mass-market adoption is possible. Then, the talk will focus on three challenges for these systems: compute-in-memory architectures, AI compilers and hardware security. In the final part of the talk, we will introduce our proposed solution for an integrated system design. We are convinced that efficient, widely adopted CIM systems will only be possible if they are integrated into existing edge-AI software stacks. Otherwise, seamless and risk-free migration from existing CMOS technology will not be attractive or realistic for companies, even though emerging memories offer substantial power savings. Therefore, it is imperative to provide an ecosystem of software and hardware development kits that work with existing edge-ML tools.
Dr. Joseph holds a tenured position as senior researcher at the RWTH Aachen University. He leads a team researching compilers, architectures, and security for computing-in-memory-based edge AI accelerators. He and his team won the RWTH innovation award for the universities best transfer-to-industry project in 2022. From 2020 to 2022, he was a postdoctoral research fellow in Aachen and led an industry project on parallel simulation with gem5. From 2019 to 2020 Dr. Joseph was a visiting researcher at Dr. Krishna’s Synergy Lab at Georgia Institute of Technology, Atlanta, GA. He worked on architectures for AI accelerators. For his PhD on "Networks-on-Chip for heterogeneous 3D Systems-on-Chip" he received the award for the best PhD thesis from the Faculty of Electrical Engineering and Information Technology at Otto-von-Guericke Universität Magdeburg, Germany in 2020.