Events

Processes for the “Chemical Engineering-ification” of Electronics

Academic,
Seminar / Lecture
 
For NYU Community

Michael A. Filler

Speaker:

Michael A. Filler
School of Chemical & Biomolecular Engineering Georgia Institute of Technology

Abstract:

This talk will overview our recent efforts to bring about the ‘chemical engineering-ification’ of electronics. While chemical engineering has played a major role in the development and success of integrated circuitry, the process by which we manufacture integrated circuits – the planar process – is strikingly antithetical to the foundational tenets of chemical engineering. In planar processing, electronic devices are constructed and interconnected on semiconductor wafers using atomic/molecular building blocks. There are no intermediate products and, relatedly, no intermediate separations. The monolithicity, seamlessness, and 2-D nature of planar processing can generate remarkably complex circuitry; however, it also places significant restrictions on cost, throughput, and functional diversity.

To overcome these limitations, we are developing a suite of processes to modularize nanoelectronic de- vices and hyper-scale their manufacturing. Modularization at the device level promises an unprecedented combination of performance, cost, and function and, as a result, new electronic capabilities such as on-demand or reconfigurable integrated circuits. ‘Nano-modular’ device fabrication leverages three bottom-up processes: (i) vapor-liquid-solid semiconductor

nanowire growth, (ii) a new nanoscale polymer masking process, and (iii) area-selective atomic layer deposition. Our approach yields single-crystalline, high mobility nanowires with nanoscale coaxial dielectric and metal thin films self-aligned to the internal dopant profile. In parallel, we are developing the Geode process to increase manufacturing throughput by several orders of magnitude. This scale-up is made possible by an unconventional substrate – the interior sur- face of hollow silica microcapsule powders – on which nanowire growth and subsequent processing occur. Collaborative efforts are also enabling nanowire property characterization in a high-throughput, non-contact fashion and high-resolution interconnection of nano- modular devices to form functional circuitry.