Ramesh   Karri

Ramesh Karri

Professor

Electrical and Computer Engineering

Biography

Ramesh Karri is a Professor of Electrical and Computer Engineering at Tandon School of Engineering, New York University. He has a Ph.D. in Computer Science and Engineering, from the University of California at San Diego. His research and education activities span hardware cybersecurity including trustworthy ICs, processors and cyberphysical systems; security-aware computer aided design, test, verification, validation and reliability; nano meets security; metrics; benchmarks; hardware cybersecurity competitions; additive manufacturing security.

He has over 200 journal and conference publications including tutorials on Trustworthy Hardware in IEEE Computer (2) and Proceedings of the IEEE (5). His groups work on hardware cybersecurity was nominated for best paper awards (ICCD 2015 and DFTS 2015) and received awards at conferences (ITC 2014, CCS 2013, DFTS 2013 and VLSI Design 2012) and at competitions (ACM Student Research Competition at DAC 2012, ICCAD 2013, DAC 2014, ACM Grand Finals 2013, Kaspersky Challenge and Embedded Security Challenge).

He was the recipient of the Humboldt Fellowship and the National Science Foundation CAREER Award. He is the area director for cyber security of the NY State Center for Advanced Telecommunications Technologies at NYU-Poly; Co-founded the NYU Center for CyberSecurity  -CCS (http://cyber.nyu.edu/), co-founded the Trust-Hub (http://trust-hub.org/) and founded and organizes the Embedded Security Challenge, the annual red team blue team event at NYU,  (http://www.nyu.edu/csaw2016/csaw-embedded).

He co-founded the IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH). He served as program/general chair of conferences including IEEE International Conference on Computer Design (ICCD), IEEE Symposium on Hardware Oriented Security and Trust (HOST),  IEEE Symposium on Defect and Fault Tolerant Nano VLSI Systems (DFTS) NANOARCH, RFIDSEC 2015 and WISEC 2015. He serves on several program committees (DAC, ICCAD, HOST, ITC, VTS, ETS, ICCD, DTIS, WIFS).

He was the Associate Editor of IEEE Transactions on Information Forensics and Security (2010-2014), IEEE Transactions on CAD (2014-present), ACM Journal of Emerging Computing Technologies (2007-present), ACM Transactions on Design Automation of Electronic Systems (2014-present), IEEE Access (2015-present), IEEE Transactions on Emerging Technologies in Computing (2015-present), IEEE Design and Test (2015-present) and IEEE Embedded Systems Letters (2016-present). He served as an IEEE Computer Society Distinguished Visitor (2013-2015). He is on the Executive Committee of IEEE/ACM Design Automation Conference initiating and leading the Security@DAC initiative (2014-2017). He has delivered invited keynotes, talks, and tutorials on Hardware Security and Trust (ESRF, DAC, DATE, VTS, ITC, ICCD, NATW, LATW, CROSSING etc).

Education

University of California, San Diego, 1993

Doctor of Philosophy, Computer Science

University of California, San Diego, 1992

Master of Science, Computer Engineering

University of Hyderabad, 1988

Master of Technology, Computer Science

Andhra University, 1985

Bachelor of Engineering, Electronics and Communication Engineering

Experience

New York University

Professor

Research and teaching in computer engineering. Current research focus is on trustworthy and secure hardware.

From: September 2011 to present

Polytechnic Institute of New York University

Associate Professor

Research and teaching in computer engineering. Current research focus is on trustworthy and secure hardware.

From: September 1998 to August 2011

University of Massachusetts, Amherst

Assistant Professor of Electrical and Computer Engineering

Research and teaching in computer engineering.

From: September 1993 to July 1998

Lucent Bell Labs Engineering Research Center, Princeton

Member of Technical Staff

On-line built-in self test of VLSICs

From: June 1997 to July 1998

University of California, San Diego

Graduate Teaching and Research Assistant

From: September 1989 to August 1993

Fifth Generation Computing Group, CMC Research and Development Ce

Research Engineer

Implemented multiprocessor cache consistency protocols and evaluated their performance and scalability.

From: May 1988 to June 1989