Ramesh   Karri

Ramesh Karri

Professor

Electrical and Computer Engineering

Biography

Ramesh Karri (http://eeweb.poly.edu/karri/) is a Professor of Electrical and Computer Engineering at New York University Polytechnic School of Engineering. He has a Ph.D. in Computer Science and Engineering from the University of California at San Diego. His research interests include trustworthy hardware (integrated circuits to processor architectures); High assurance nanoscale integrated circuits, architectures, and systems; VLSI Design and Test; Interaction between security and reliability.

He has over 150 journal and conference publications. He has written two invited articles in IEEE Computer on Trustworthy Hardware, an invited article on Digital Logic Design using Memristors in Proceedings of IEEE and an Invited article in IEEE Computer on Reliable Nanoscale Systems. 

He is the recipient of the Humboldt Fellowship and the National Science Foundation CAREER Award. He is the area director for cyber security of the NY State Center for Advanced Telecommunications Technologies at NYU School of Engineering; Hardware security lead of the Center for research in interdisciplinary studies in security and privacy -CRISSP (http://crissp.poly.edu/), co-founder of the Trust-Hub (http://trust-hub.org/) and organizes the annual red team blue team event at NYU, the Embedded Systems Security Challenge (http://www.poly.edu/csaw2012/csaw-embedded).

He co-founded and served as the chair of the IEEE Computer Society Technical Committee on Nanoscale architectures. He co-founded and serves on the steering committee of the IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH). He served as  the Program Chair and General Chair of several conferences including IEEE Symposium on Hardware Oriented Security and Trust (HOST),  IEEE Symposium on Defect and Fault Tolerant Nano VLSI Systems, IEEE/ACM NANOARCH. He serves on several program committees including DAC, VTS, ICCD, HOST, DFT, DTIS, and NANOARCH. He is the Associate Editor of IEEE Transactions on Information Forensics and Security, IEEE Transactions on CAD, and ACM Journal of Emerging Technologies in Computing. He is a IEEE Computer Society Distinguished Visitor 2013-2014.

He organized/delivered invited tutorials on Trustworthy Hardware (including 2012 IEEE VLSI Test Symposium 2012, IEEE International Conference on Computer Design 2012, IEEE North Atlantic Test Workshop 2013, Design Automation and Test in Europe 2013, IEEE International Test Conference 2013, IEEE Latin American Test Workshop 2014, IEEE/ACM Design Automation Conference 2014, and IEEE ).

Education

University of California, San Diego, Class of 1993

Doctor of Philosophy, Computer Science

University of California, San Diego, Class of 1992

Master of Science, Computer Engineering

University of Hyderabad, Class of 1988

Master of Technology, Computer Science

Andhra University, Class of 1985

Bachelor of Engineering, Electronics and Communication Engineering

Experience

New York University

Professor

Research and teaching in computer engineering. Current research focus is on trustworthy and secure hardware.

From: July 1998 to present

University of Massachusetts, Amherst

Assistant Professor of Electrical and Computer Engineering

Research and teaching in computer engineering.

From: September 1993 to July 1998

Lucent Bell Labs Engineering Research Center, Princeton

Member of Technical Staff

On-line built-in self test of VLSICs

From: June 1997 to July 1998

University of California, San Diego

Graduate Teaching and Research Assistant

From: September 1989 to August 1993

Fifth Generation Computing Group, CMC Research and Development Ce

Research Engineer

Implemented multiprocessor cache consistency protocols and evaluated their performance and scalability.

From: May 1988 to June 1989

Research Interests

  • Trustworthy Hardware
  • Nanoscale Architectures
  • Nano-enabled Security and Assurance
  • Computer Aided Design of Fault-Tolerant VLSI systems