Jonathan   Chao

Jonathan Chao

Department Head

Electrical & Computer Engineering

Biography

H. Jonathan Chao, a recognized expert in high-performance routers, is department head and professor in the Department of Electrical and Computer Engineering. He joined the NYU-Poly faculty in 1992.

His research is focused in the areas of terabit switches/routers, network security, network on the chip, and quality of service control in high-speed networks. He holds 28 patents with 17 pending and has published over 180 journal and conference papers. He has also served as a consultant for various companies, such as Huawei, Lucent, NEC, and Telcordia.

Chao is the co-founder and former CTO of Coree Networks, where he led a team in implementing a multi-terabit Multi-Protocol Label Switching (MPLS) switch router with carrier-class reliability. He helped raise $30 million for the first round of implementation. From 1985 to 1992, he was a member of technical staff at Telcordia, where he was involved in transport and switching system architecture designs and Application-specific Integrated Circuits (ASIC) implementations. He was a senior engineer at Telecommunication Labs of Taiwan performing circuit designs for a digital telephone switching system from 1977 to 1981.

He is a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) for his contributions to the architecture and application of VLSI circuits in high-speed packet networks and was elected Speaker of the Year by IEEE New Jersey Coast Section in 2003. Chao was the 1987 recipient of the Telcordia Excellence Award and a co-recipient of the 2001 Best Paper Award from the IEEE Transaction on Circuits and Systems for Video Technology.  He coauthored three networking books, Broadband Packet Switching Technologies—A Practical Guide to ATM Switches and IP Routers (New York: Wiley, 2001), Quality of Service Control in High-speed Networks (New York: Wiley, 2001), and High-performance Switches and Routers (New York: Wiley, 2007).

He has served as a guest editor for the IEEE’s Journal on Selected Areas in Communications (JSAC) on the special topics of  “Advances in ATM Switching Systems for B-ISDN” (June 1997), “Next Generation IP Switches and Routers” (June 1999), two issues on “High-performance Optical/Electronic Switches/Routers for High-speed Internet” (May and September 2003), and “High-speed Network Security” (October 2006). He also served as an editor for IEEE/ACM Transactions on Networking from 1997–2000.

Chao earned his bachelor’s and master’s in electrical engineering from National Chiao Tung University, Taiwan, and his PhD in Electrical Engineering from Ohio State University.
 

Journal Articles

  • M. Bando, S. Artan, and H. J. Chao, “FlashLook: 100-Gbps Hash-Tuned Route Lookup Architecture,” IEEE Workshop on High Performance Switching and Routing, Paris, June 2009.
  • M. Rodelgo-Lacruz, C. López-Bravo, F. J. González-Castaño, and H. J. Chao, “Practical Scalability of Wavelength Routing Switches” in IEEE ICC, Germany, June 2009.
  • S. Artan, H. Yuan, and H. J. Chao, “A Dynamic Load-Balanced Hashing Scheme for Networking Applications,” IEEE Globecome, New Orleans, LA, Nov. 2008.
  • M. Bando, S. Artan, and H. J. Chao, “Highly Memory-Efficient LogLog Hash for Deep Packet Inspection,” IEEE Globecome, New Orleans, LA, Nov. 2008.
  • H, Sun, Y, Zhuang, and H. J. Chao, “A Principal Components Analysis-based Robust DDoS Defense System,” IEEE ICC, Beijing, May 2008.

Education

The Ohio State University

Doctor of Philosophy, Electrical Engineering

National Chiao Tung University

Master of Science, Electrical Engineering

National Chiao Tung University

Bachelor of Science, Electrical Engineering

Awards + Distinctions

  • Elected to be Speaker of the Year by IEEE New Jersey Coast Section, April 2003.
  • Elected to be Fellow of IEEE for contributions to the architecture and application of VLSI circuits in high-speed packet networks in January 2001.
  • Co-recipient of the journal's best paper award of 2001 IEEE Transactions on Circuits and Systems for Video Technology.
  • Received Bellcore Excellence Award in March 1987 for designing the first SONET-like Frame chip running up to 200 Mbit/s using CMOS 2-m technology.

Research Interests

  • Network Security
  • High Performance Routers

General / Collaborative Research

Project title: Novel Medical Device for Preventing Epileptic Seizures (NYU)CO-PI: Nandor Ludvig (Dept. of Neurology, Comprehensive Epilepsy Center, NYU School of Medicine) and H. Jonathan Chao (Dept. of Electrical and Computer Engineering, Polytechnic Institute of NYU)

Grants

Development and Demonstration of a High Performance Computing Sys, (CO-PI: G. Rose, H. J. Chao, and K. Xi)

Army Research Lab, 9/209 - 8/2010 (2 years)

Amount: $800,000