Architectures for Message-Passing Decoders

Monday, April 8, 2013 - 11:00am - 12:00pm EDT

  • Location:10th Floor, Room 10.099
    Two Metrotech Center, BROOKLYN, New York, US

Speaker: Warren Gross

Host Faculty: Professor Elza Erkip

Abstract

Error-correcting decoders based on message-passing algorithms over graphs are fundamental building blocks in modern communications and data storage systems. In this talk I will present recent results in developing architectures and implementations for high-throughput and low-power message-passing decoders. The talk will be divided into two parts: designing hardware for coding, and then applying coding to the design of hardware.

I will present four main architectural ideas. The first is stochastic decoding, where information is represented by the statistics of bit streams, resulting in simple, high-speed hardware implementations of graph-based decoding algorithms. Next, I will describe an architecture that allows multi-Gbps decoding of very long polar codes. I will then present an analysis of LDPC codes when the decoder is built exclusively out of faulty computing devices. and describe an extension to the Gallager-B algorithm that provides large gains in fault tolerance for a small decoding complexity overhead. Finally, I will show how concepts from message-passing decoding can be used to implement low-power network routers.

About the Speaker

Warren J. Gross received the B.A.Sc. degree in electrical engineering from the University of Waterloo, Waterloo, Ontario, Canada, in 1996, and the M.A.Sc. and Ph.D. degrees from the University of Toronto, Toronto, Ontario, Canada, in 1999 and 2003, respectively. Currently, he is an Associate Professor with the Department of Electrical and Computer Engineering, McGill University, Montreal, Quebec, Canada. His research interests are in the design and implementation of signal processing systems and custom computer architectures.

Dr. Gross is currently Vice-Chair of the IEEE Signal Processing Society Technical Committee on Design and Implementation of Signal Processing Systems and serves as Associate Editor for the IEEE Transactions on Signal Processing. He has served as Technical Program Co-Chair of the IEEE Workshop on Signal Processing Systems (SiPS 2012) and as Chair of the IEEE ICC 2012 Workshop on Emerging Data Storage Technologies. Dr. Gross is a Senior Member of the IEEE and a licensed Professional Engineer in the Province of Ontario.