Communication Challenges in Many-Core and 3-D ASICs

Wednesday, April 7, 2010 - 11:00am - 12:00pm EDT

  • Location:Dibner Building, LC 102
    NY

Speaker: Prof. Maged Ghoneima

Abstract

Today’s System-On-Chip (SoC) devices are targeting complex applications, where there is a need for significant amount of computing power and data transfer. This implies that the number of on-chip modules will increase, and so will the number of on- chip buses connecting these modules. With the continuous scaling of technology, increased die area and faster clock speeds, the delay and power dissipation of on-chip buses are becoming one of the main bottlenecks in current high-performance SoC design. The focus of this talk is to present circuit techniques that reduce the power dissipation, induced noise, and delay of on-chip buses in the current many-core ASICs and in the future 3D ASICs.

About the Speaker

Maged Ghoneima received a BSc (with honors) degree in electronics and communications engineering and a MSc degree in electronics from Ain Shams University, Cairo, Egypt, in 1997 and 2000, respectively, and a PhD degree in computer engineering from Northwestern University, Evanston, IL, in 2006. In 1997, he was appointed as a Teacher Assistant at the Department of Electrical and Computer Engineering, Ain Shams University. During 2002, he was
with OEA International and with the Circuit Research Laboratory, Intel Corporation, from 2003 to 2005. He has been with the Custom VLSI Circuit Design Group, NVIDA Corporation, Santa Clara, CA, as currently a Senior Circuit Design Engineer, developing on-chip memory structures for the Tesla and Fermi graphics processing units (GPUs) since 2006. Starting 2010, Dr. Maged has joined the Nanoelectronics Integrated Systems Center at Nile University as an Assistant Professor. He is the author or coauthor of more than 25 technical papers published in refereed international conferences and journals. He holds two granted patents and more than five patents filed in the area of low-power and high-performance circuit design. His current research interests include on-chip interconnect architectures, on-chip memory structures, low-power circuit design, MEMS and 3D-IC integration. Dr. Maged was a recipient of the Walter Murphy and Capell Fellowship awards from Northwestern University in 2001 and 2005, and the Intel PhD Fellowship Award in 2004.