Design-for-Testability and Cost-Effective Testing of SOCs

Thursday, March 25, 2010 - 11:00am - 12:00pm EDT

  • Location:Dibner Building, LC400
    5 MetroTech Center

    Brooklyn, New York
  • Price:

Speaker: Professor Ozgur Sinanoglu



While the system-on-a-chip (SOC) design style has successfully ameliorated the effort required in designing sizable chips, the test costs have been significantly exacerbated, necessitating aggressive design-for-testability (DfT) solutions. Integration of pre-designed, pre-verified cores within the same die offers design re-use benefits, thus shortening time-to-market, while the particular test strategy to be employed hinges on the business model that dictates the design of the SOC. Utilization of all in-house cores in an SOC enables the merging of all these core netlists into one SOC netlist, for which both test generation and application can be effected monolithically. An SOC with third party cores, on the other hand, necessitates a different test approach, as these cores may have been delivered with their logic structure concealed due to Intellectual Property (IP) considerations of their vendors. In this case, a set of test patterns are also provided along with each encapsulated core, and the SOC integrator should implement an on-chip test access mechanism to be able to apply the provided test set at the interface of each core, resulting in a modular testing scheme.

Monolithic and modular testing strategies necessitate fundamentally different DfT techniques. In monolithic testing, a generic hardware solution that is resilient to late design changes is required, while DfT solutions customized based on given core tests is the key to minimizing test costs in modular testing. In this talk, we present a series of DfT solutions for each of the two testing strategies. In particular, we propose an OCD scan architecture that addresses the challenges in the context of monolithic testing by providing ultimate control over test pattern delivery, response observation, and power dissipation during test. These three fundamental problems of test are mitigated by the on-chip transformation framework we propose in the context of modular testing.

About the Speaker

Dr. Ozgur Sinanoglu obtained his BS degrees in electrical and electronics engineering and in computer engineering from Bogazici University, Turkey, in 1999. He obtained his MS and PhD degrees in the Computer Science and Engineering Department, University of California, San Diego, in 2001, and 2004, respectively. During his PhD studies, he received the "IBM PhD Fellowship Award" twice, and the "CSE PhD Dissertation Award" at UC San Diego. Between 2004 and 2006, he worked as a senior DfT engineer at Qualcomm, San Diego. Since Fall 2006, he has been a faculty member with the Department of Mathematics and Computer Science, Kuwait University. Recently, he received two research awards including the "Best Young Researcher Award" at Kuwait University. His research interests include Computer-Aided Design (CAD) and reliability of VLSI circuits, and in particular SOCs.