Seminar: NATURE - A Hybrid NanoRAM/CMOS Dynamically Reconfigurable Architecture
Speaker: Professor Niraj K. Jha
Faculty Host: Prof. Hai (Helen) Li
Abstract
As CMOS technology approaches its physical limits, a tremendous amount of effort is being devoted to nanotechnology research in order to enable future technology scaling. Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet mature, making implementation of such circuits, at least on a large scale, in the near future infeasible. However, if photo-lithography could be used to implement circuits using these nanodevices, then hybrid nano/CMOS chips could be fabricated immediately. In this talk, we will discuss a high-performance reconfigurable architecture, called NATURE, which utilizes CMOS logic and nanoRAMs (such as nanotube RAM, phase-change memory, magnetoresistive RAM or embedded DRAM). Use of the highly-dense nanoRAMs allows significant on-chip configuration storage, enabling fine-grain (even cycle-by-cycle) temporal logic folding of a circuit before being mapped to the architecture. This can significantly increase the logic density of NATURE (by over an order of magnitude) at the same technology node relative to traditional reconfigurable architectures, while remaining competitive in performance and power consumption.
We will also present an integrated design and optimization platform for NATURE, called NanoMap. Given a mixed RTL/gate-level design, NanoMap optimizes and implements the design in NATURE through logic mapping, temporal clustering, placement, and routing. NanoMap can automatically explore and identify the best temporal logic folding configuration, targeting area, delay or area-delay product as the optimization objective. Experimental results demonstrate that NanoMap can reduce the area-delay product of a design by over an order of magnitude, and effectively exploit the different features of NATURE.
About the Speaker
Niraj K. Jha received his B.Tech. degree in Electronics and Electrical Communication Engineering from Indian Institute of Technology, Kharagpur, India in 1981 and Ph.D. degree in Electrical Engineering from University of Illinois at Urbana-Champaign in 1985. He is a Professor of Electrical Engineering at Princeton University. He is a Fellow of IEEE and ACM. He has co-authored four books, the most recent being Switching and Finite Automata Theory, 3rd Ed. with Zvi Kohavi. He is the editor-in-chief of TVLSI and serves on the editorial boards of TCAD, TCAS I, and several other journals. He is a co-author of 13 award-winning papers. His research interests include nanotechnology, embedded system analysis and design, power/thermal aware hardware/software design, computer-aided design of ICs and systems, computer security, and digital system testing.