Polytechnic Institute of New York University2014
PhD, Electrical and Computer Engineering
Polytechnic Institute of New York University2009
Master of Science, Electrical and Computer Engineering
Visveswaraya Technological Univesirty2006
Bachelor of Engineering, Electronics and Computer Engneering
IBM
Intern
Developed an Empirical model to simulate the variation and behavior of a Phase-change memory
From: June 2012 to December 2012
Journal Articles
Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, "Sneak-path Testing of Crossbar-based Non-Volatile Random Access Memories", IEEE Transactions on Nanotechnology, 2013.
Aamir Zia, Sachhidh Kannan, H. Jonathan Chao, Garrett S. Rose, "3D Network-on-Chip for many-core processors", Elsevier Microelectronics Journal, Vol: 42, Iss: 12, pp: 1380 – 1390, December, 2011.
Other Publications
Sachhidh Kannan, Naghmeh Karimi, Ramesh Karri and Ozgur Sinanoglu, "Secure Memristor-based Main Memory," Design Automation Confreence, 2014.
Sachhidh Kannan, Naghmeh Karimi, Ramesh Karri and Ozgur Sinanoglu, "Detection, Diagnosis and Repair of Faults in Memristor-based Memories," IEEE VLSI Test Symposium, 2014.
Sachhidh Kannan, Ramesh Karri and Ozgur Sinanoglu, "Sneak path Testing and Fault Modeling for Multilevel Memristor-based Memories," IEEE International Conference on Computer Design, 2013.
Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri and Ozgur Sinanoglu, "Sneak-path Testing of Memristor-based Memories," International Conference on VLSI Design, 2013.
Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri and Ozgur Sinanoglu, "Engineering Crossbar based Emerging Memory Technologies," IEEE International Conference on Computer Design, 2012.
Sachhidh Kannan, Garrett S. Rose, "A Hierarchical 3-D Floorplanning Algorithm for Many-Core CMP Networks," IEEE International Symposium on Circuits and Systems, 2011.
A. Zia, Sachhidh Kannan, Garrett S. Rose, H. J. Chao “Highly-Scalable 3D CLOS NOC for Many-Core CMPs,” NEWCAS 2010.
Research Interests
Memory Security
Non-volatile Memory Technologies
Testing and optimization of phase change memories and resistive RAMs
3D Integration of NoCs
Affiliations
IEEE Student Member
Awarded IBM Great Minds Internship 2012.
Awarded Dean's Scholarship – Polytechnic University (Spring - Fall 2007, Spring 2008).