Kanad Basu

Assistant Research Professor

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Kanad Basu is an  Assistant Research Professor at NYU Tandon school of Engineering. Kanad received his Ph.D. from the department of Computer and Information Science and Engineering, University of Florida. His thesis was focused on improving signal observability for post-silicon validation. Post-Phd, Kanad worked in various semiconductor companies like IBM and Synopsys. At IBM, he was responsible for the design on IBM Power and Z Processors. At Synopsys, Kanad helped in development of DFTMAX Ultra, the state of the art low pin hardware test solution. During his Ph.D. days, Kanad did internships at Intel. Currently, Kanad is an Assistant Research Professor at the Electrical and Computer Engineering Department of NYU. He has authored 2 US patents, 2 book chapters and several peer reviewed journal and conference articles. Kanad was awarded the "Best Paper Award" at the International Conference on VLSI Design 2011.

Recent Updates:

[02/01/19] Our paper titled "PREEMPT: PReempting Malware by Examining Embedded Processor Traces" has been accepted for publication  at  ACM Design Automation Conference, 2019. 

[01/25/19] Our  paper titled "Towards Increasing the Difficulty of Reverse Engineering of RSFQ Circuits", has been accepted for publication at IEEE Transactions on Applied Superconductivity.

[01/15/19] Our research on Hardware assessment of  Post-Quantum Cryptography algorithms  is  available  online. Please see our webpage or read our paper

[12/10/18] Our research proposal (Kanad Basu as co-PI) titled "MIDAS TOUCH: Malware Identification in Driver Assistance Systems by Tracking On-chip Unhackable Counter Hardware”, has been provisionally accepted by Ford Motors. Thanks Ford!!

[11/19/19]  Our paper titled  "Black-Hat High-Level Synthesis: Myth or Reality?" has been accepted for  publication at IEEE Transactions on VLSI Systems

[11/08/19]  Our  paper titled "High-Level Synthesis of Benevolent Trojans"  has been accepted for publication at International Conference on Design and Test in Europe, 2019.

[10/18/18] Our  paper titled "Post-Silicon Gate-Level Error Localization with  Effective & Combined Trace Signal Selection" has been accepted for  publication at IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems.

[09/23/19] Our paper titled "Efficient Post-Silicon Validation of Network-on-Chip using Wireless Links" has been accepted for publication at International Conference on VLSI Design,  2019

[07/09/18] Our paper titled "Abetting Planned Obsolescence by Aging 3D Networks-on-Chip" has been accepted for publication at International Symposium on Network on Chips,  2018.

[09/01/17] Joined  NYU as an Assistant Research Professor.


University of Florida 2012
Ph.D., Computer Engineering

University of Florida 2012
Master of Science, Computer Engineering

Jadavpur University, India 2007
Bachelor of Engineering, Electronics and Telecommunication Engineering

 


New York University
Assistant Research Professor
From: September 2017 to present

Synopsys Inc
Senior R&D Engineer
From: September 2013 to August 2017

IBM
Staff R&D Engineer
From: August 2012 to September 2013

Intel
Graduate Intern
From: May 2011 to August 2011
 
Intel
Graduate Intern
From: May 2008 to August 2008

 


Summary of Publications

2 book chapters, 10 journal articles (4 under review), 28 referred conference papers and workshop proceedings (2 under review), 2 patents, 1 tutorial, 2 thesis dissertations.

Selected Publications

(For full list of publications, please see my Google Scholar profile: https://scholar.google.com/citations?user=q0PDoH8AAAAJ&hl=en)

Book Chapters:

[1] Kanad Basu. Structural Signal Selection for Post-Silicon Validation, In: Post-Silicon Validation and Debug, Springer, 2018.

[2] Nirmalya Bandyopadhyay, Kanad Basu and Prabhat Mishra. HMDES, ISDL and Other Contemporary ADLs, In: Processor Description Languages: Applications and Methodologies, Morgan Kaufmann Publishers, 2008.

Journal Articles:

[3] Kanad Basu, Prashanth Krishnamurthy, Farshad Khorrami and Ramesh Karri. A Theoretical Study of Hardware Performance Counters-based Malware Detection. IEEE Transactions on Information Forensics and Security (TIFS), 2018 [Under Review].

[4] Kanad Basu, Samah Saeed, Christian Pilato, Mohammad Ashraf, Mohammad Nabeel, Krishnendu Chakraborty and Ramesh Karri. CAD-Base: An Attack Vector into the Electronics Supply Chain. ACM Transactions on Design Automation of Embedded Systems (TODAES), 2018 [Under Review after major revision].

[5] Jeff Zhang, Kanad Basu and Siddharth Garg. Fault-tolerant Systolic Array Based Accelerators for Deep Neural Network Execution. IEEE Design and Test of Computer (DNT), 2018 [Under Review after major revision].

[6] Mohammad Shayan, Kanad Basu and Ramesh Karri. Hardware Trojans Inspired IP Watermarks. IEEE Design and Test of Computer (DNT), 2018 [Under Review after major revision].

[7] Christian Pilato, Kanad Basu and Ramesh Karri. Black-Hat High-Level Synthesis: Myth or Reality? Accepted at IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2019.

 [8] Harshit Kumar, Tahereh Jabberi, Gleb Krylov, Kanad Basu, Eby Friedman, and Ramesh Karri. Super secure? security analysis of superconducting electronics. Accepted for publication at IEEE Transactions on Applied Superconductivity, 2019.

 [9] Binod Kumar, Kanad Basu, Masahiro Fujita and Virendra Singh. Post-Silicon Gate-Level Error Localization with Effective & Combined Trace Signal Selection. Accepted for publication in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 2018.

[10] Kanad Basu, Chetan Murthy and Prabhat Mishra. Bitmask aware compression of NISC Control Words. Integration, the VLSI Journal (Elsevier), 2013.

[11] Kanad Basu and Prabhat Mishra. Restoration Aware Trace Signal Selection for Post-silicon Validation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2013.

[12] Kanad Basu and Prabhat Mishra. Test Data Compression using Efficient Bitmask and Dictionary Selection Methods. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2009.

 

Peer-Reviewed Conference and Workshop Proceedings:

[13] Kanad Basu, Deepraj Soni, Mohammad Nabeel, and Ramesh Karri. NIST Post-Quantum Cryptography-A Comprehensive Hardware Evaluation. IACR Conference on Cryptographic Hardware and Embedded Systems (CHES), 2019. [Under Review]

 [14] Kanad Basu, Suha Hussain, Ujjwal Gupta, and Ramesh Karri. HPCA: HPC-based COPPA violations Analyzer. USENIX Symposium on Usable Privacy and Security (SOUPS), 2019. [Under Review]

[15] Kanad Basu, Rana Elnaggar, Krishnendu Chakrabarty, and Ramesh Karri. Preempt: PReempting malware by Examining Embedded Processor Traces. Accepted for publication at ACM/IEEE Design Automation Conference (DAC), 2019.

[16] Chistian Pilato, Kanad Basu, Mohammed Shayan, Francesco Regazzoni and Ramesh Karri. High-Level Synthesis of Benevolent Hardware Trojans for IP Watermarking. Accepted for publication at Design, Automation and Test in Europe Conference (DATE), 2019.

[17] Sidhartha Sankar Rout, Kanad Basu and Sujay Deb. Efficient Post-Silicon Validation of Network-on-Chip using Wireless Links. IEEE International Conference on VLSI Design (VLSID), 2019.

[18] Jeff Zhang, Tianyu Gu, Kanad Basu and Siddharth Garg. Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator. IEEE VLSI Test Symposium (VTS), 2018.

[19] Binod Kumar, Kanad Basu and Virendra Singh. A Technique for Electrical Error Localization with Learning Methods During Post-silicon Debugging. IEEE International Conference on Green and Sustainable Computing (IGSCC), 2018.

[20] Sourav Das, Kanad Basu, Janardhan Rao Doppa, Partha Pratim Pande, Ramesh Karri, Krishnendu Chakrabarty. Abetting Planned Obsolescence by Aging 3D Networks-on-Chip. IEEE International Symposium on Network on Chips (NOCS), 2018.

[21] Ankit Jindal, Binod Kumar, Kanad Basu, and Masahiro Fujita. ELURA: A Methodology for Post-silicon Gate-level Error Localization using Regression Analysis. IEEE International Conference on VLSI Design (VLSID), 2018.

[22] Binod Kumar, Kanad Basu, Masahiro Fujita and Virendra Singh. RTL Level Trace Signal Selection and Coverage Estimation During Post-Silicon Validation. IEEE International High Level Design Validation and Test Workshop (HLDVT), 2017.

[23] Binod Kumar, Kanad Basu, Ankit Jindal, Masahiro Fujita, and Virendra Singh. Improving post-silicon error detection with topological selection of trace signals. IEEE/IFIP International Conference on on Very Large Scale Integration (VLSI-SoC), 2017.

[24] Kanad Basu, Rishi Kumar, Santosh Kulkarni and Rohit Kapoor. Deterministic Shift Power Reduction in Test Compression. IEEE International Symopsium on VLSI Design and Test (VDAT), 2017.

[25] Binod Kumar, Kanad Basu, Ankit Jindal, Brajesh Pandey and Masahiro Fujita. A Formal Perspective on Effective Post-Silicon Debug and Trace Signal Selection. IEEE International Symopsium on VLSI Design and Test (VDAT), 2017.

[26] Subhadip Kundu, Kanad Basu and Rohit Kapur. Observation-Point identification based on Signal Selection Methods for improving Diagnostic Resolution. International Test Conference – India (ITC-India), 2017.

[27] Kanad Basu, Prabhat Mishra, Priyadarsan Patra, Amir Nahir, Allon Adir. Dynamic Selection of Trace Signals for Post-Silicon Debug. International Workshop on Microprocessor Test and Verification (MTV), 2013.

[28] Kanad Basu, Prabhat Mishra and Priyadarsan Patra. Observability-aware Directed Test Generation for Soft Errors and Crosstalk Faults. IEEE International Conference on VLSI Design (VLSID), 2013.

[29] Kanad Basu, Prabhat Mishra and Priyadarsan Patra. Constrained Signal Selection for Post Silicon   Validation. IEEE International High Level Design, Validation and Test Workshop (HLDVT), 2012.

[30] Kanad Basu, Prabhat Mishra and Priyadarsan Patra. Efficient Combination of Trace and Scan Signals for Post-Silicon Validation and Debug. IEEE International Test Conference (ITC), 2011.

[31] Kanad Basu and Prabhat Mishra. Efficient Trace Data Compression using Statically Selected Dictionary. IEEE VLSI Test Symposium (VTS), 2011.

[32] Kanad Basu and Prabhat Mishra. Efficient Trace Signal Selection for Post Silicon Validation and Debug. International Conference on VLSI Design (VLSID), 2011 (Best Paper Award).

[33] Kanad Basu and Prabhat Mishra. A Novel Test-Data Compression Technique using Application-Aware Bitmask and Dictionary Selection Methods. ACM Great Lakes Symposium on VLSI (GLSVLSI), 2008.

Patents:

[34] Kanad Basu, Raghu Gaurav Gopalakrishnasetty and Hari Krishnan Rajeev. Automatic test pattern generation (ATPG) considering crosstalk effects. US9218447B2

[35] Prabhat Mishra, Seok-won Seong, Kanad Basu, Weixun Wang, Xiaoke Qin. Bitmaksk-based Code Compression Technique and Decompression Mechanism. Provisional Patent UF 12654, 2007.

Tutorials:

[36] Kanad Basu and Subhadip Kundu. Post-Silicon Validation and Diagnosis. IEEE International Conference on VLSI Design, 2016.

Thesis:

[37] Kanad Basu. Efficient Techniques for Observability Enhancement during Post-Silicon Validation. Doctoral Dissertation, University of Florida, 2012.

[38] Kanad Basu. Simulation of radiotherapy treatment for brain tumors on MRI images. Bachelors project, Jadavpur University, 2006.

 

 


  • Nominated for Blavatnik Awards for Young Scientists, 2019.
  • Quarterly Achievement Award, 2015 fourth quarter, Synopsys Inc.
  • Best Paper Award at the International Conference on VLSI Design 2011.
  • College of Engineering Travel grant for attending IEEE VLSI Test Symposium, 2011.
  • CISE Departmental Travel grant for attending IEEE International Test Conference, 2011.
  • Outstanding Student Achievement Award from University of Florida Internal Center for the years 2008 and 2010.
  • CISE Departmental Travel Grant for attending ACM Great Lakes Symposium on VLSI, 2008.
  • Scholarship from National Brain Research Center (NBRC), India for summer internship at NBRC, 2006 (14 students all across India were selected for the scholarship).
  • Ranked 23rd (engineering stream) in the West Bengal Joint Entrance Examination (among 170,000 examinees) in 2003.