Shaloo  Rakheja, PhD

Shaloo Rakheja, PhD

Assistant Professor, Electrical and Computer Engineering

Publications

Book chapters and magazine articles

  • S. Rakheja, A. Ceyhan, and A. Naeemi, “Interconnect Considerations”, to appear in CMOS and Beyond: Logic Switches for Terascale Integrated Circuits, Cambridge  University Press, 2013.
  • S. Rakheja and A. Naeemi, “Communicating novel computational state variables in post-CMOS logic”, IEEE Nanotechnology Magazine, vol. 7, no. 1, 2013.
  • S. Rakheja and A. Naeemi, “On physical limits and challenges of graphene   nanoribbons as interconnects for all-spin logic” in Nanoelectronic Device Applications Handbook, James Morris and Krzysztof Inieweski (Eds.), CRC Press, 2012.
  • S. Rakheja and A. Naeemi, “Interconnects for Alternative State Variables”, in   Graphene Nanolectronics, R. Murali (Ed.), Springer, 2011.
  • Contributed to the chapter  “Emerging Interconnects” in International Technology Roadmap for Semiconductors (ITRS), 2011.

Journal papers

  • S. Rakheja and P. Sengupta, "Gate voltage tunability of plasmons in single- and multi-layer graphene structures - analytical description and concepts for THz devices," submitted to IEEE Transactions on Nanotechnology. Also available at: http://arxiv.org/abs/1508.00658
  • S. Rakheja and P. Sengupta, "The tuning of light-matter coupling and dichroism in graphene for enhanced absorption: Implications for graphene-based optical absorption devices," submitted to Journal of Applied Physics. Also available at: http://arxiv.org/pdf/1506.04308.pdf
  • S. Rakheja, M. LundstromD. Antoniadis, “An Improved Virtual-Source-Based Transport Model for Quasi-Ballistic Transistors – Part I: Capturing Effects of Carrier Degeneracy, Drain-Bias Dependence of Gate Capacitance, and Non-linear Channel-Access Resistance," accepted for publication in IEEE Transactions on Electron Devices.
  • S. Rakheja, M. Lundstrom, D. Antoniadis, "An Improved Virtual-Source-Based Transport Model for Quasi-Ballistic Transistors – Part II: Experimental Verification," accepted for publication in IEEE Transactions on Electron Devices.
  • S. Rakheja, Y. Wu, H. Wang, T. Palacios, and D. Antoniadis, “An ambipolar virtual-source-based charge-current compact model for nanoscale graphene transistors,” IEEE Transactions on Nanotechnology, vol. 13, no. 5, pp. 1005-1013, Sep. 2014.
  • P. Bonhomme, S. Manipatruni, R. Mousavi, S. Rakheja, D.E. Nikonov, I.A. Young, and A. Naeemi, “Circuit simulation of magnetization dynamics and spin transport,” IEEE Transactions on Electron Devices, vol. 61, no. 5, May 2014.
  • S. Rakheja, S.-C. Chang, and A. Naeemi, “Impact of dimensional scaling and size effects on spin transport in spin valves with copper and aluminum channels,” IEEE Transactions on Electron Devices, vol. 60, no. 11, Nov. 2013.
  • S. Rakheja and A. Naeemi, “Roles of doping, temperature, and electric field on spin transport through semiconducting channels in spin valves,” IEEE Transactions on Nanotechnology, vol. 12, no. 5, Sep. 2013.
  • S. Rakheja, V. Kumar, and A. Naeemi, “Evaluation of the potential performance of graphene nanoribbon as on-chip interconnects,” Proceedings of the IEEE, vol. 101, no. 7, 2013 (invited).
  • V. Kumar, S. Rakheja, and A. Naeemi, “Performance and energy-per-bit modeling of multi-layer graphene conductors,” IEEE Transactions on Electron Devices, vol. 59, no. 10, 2012.
  • S. Rakheja and A. Naeemi, “Graphene nanoribbon spin interconnects for nonlocal spin-torque circuits: comparison of performance and energy per bit with CMOS interconnects,” IEEE Transactions on Electron Devices , vol. 59, no. 1, 2012 .
  • S. Rakheja and A. Naeemi, “Modeling Interconnects For Post-CMOS Devices and Comparison With Copper Interconnects,” IEEE Transactions on Electron Devices, vol. 58, no. 5, 2011.
  • S. Rakheja and A. Naeemi, “Communicating Novel State Variables: Physical Limits and Device and Circuit Implications,” IEEE Transactions on Electron Devices, vol. 57, no. 10, 2010.
  • S. Kar, S. Rawat, S. Rakheja, and D. Reddy, “Characterization of Accumulation Layer Capacitance for Extracting Data on High-K Gate Dielectrics,” IEEE Transactions on Electron Devices, vol. 52, no. 6, June 2005.

Conference proceedings

  • S. Rakheja and D. Antoniadis, "Physics-based compact modeling of charge transport in nanoscale electronic devices,"  IEEE Electron Devices Meeting (IEDM), Dec. 07-09, 2015 (invited).
  • S. Rakheja, "Engineering Plasmons in Graphene Nanostructures in
    THz Frequencies: Compact Modeling and Performance Analysis for On-chip Interconnects," The International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sep. 9-11, 2015. 
  • S. Rakheja, "Fundamental Limits of Energy Dissipation in Spintronic Interconnects Using Optical Spin Pumping," Nanoarch, July 8-10, 2015. 
  • S. Rakheja and P. Sengupta, "Tunability of optical absorption in a heterostructure with an embedded graphene sliver," Device Research Conference (DRC), June 21-24, 2015. 
  • L. Yu, D. El-Damak, S. Ha, S. Rakheja, X. Li, J. Kong, D. Antoniadis, A. Chandrakasan, T. Palacios, “MoS2 FET fabrication and modeling for large-scale flexible electronics,” Symposia on VLSI Technology and Circuits, June 16-18, 2015.
  • S. Rakheja, “Quasi-ballistic transport in alternate channel material devices,” CMOS Emerging Technologies Research (CMOSETR), May 20-22, 2015 (invited).
  • S. Rakheja, M. Lundstrom, and D.A. Antoniadis, “A physics-based compact model for FETs from diffusive to ballistic carrier transport regimes,” IEEE Electron Devices Meeting (IEDM), Dec. 15-17, 2014.
  • V. Kumar, S. Rakheja, and A. Naeemi, “Graphene interconnects for the end of the roadmap CMOS nanoelectronics,” IEEE International Symposium on Electromagnetic Compatibility (EMC), Aug. 03-08, 2014.
  • S. Rakheja and P. Sengupta, “Graphene nanoribbon plasmonic waveguides: fundamental limits and device implications,” Device Research Conference (DRC), June 22-25, 2014.
  • S. Rakheja and D.A. Antoniadis, “An ambipolar virtual-source-based charge-current compact model for quasi-ballistic graphene transistors applicable in analog and RF simulations,” Semiconductor Research Corporation (SRC), TECHCON, Sep. 08-09, 2014.
  • A. Naeemi, A. Ceyhan, V. Kumar, C. Pan, R. Mousavi, and S. Rakheja, “BEOL scaling limits and next generation technology prospects,” IEEE Design Automation Conference (DAC), June 02-06, 2014 (invited).
  • S. Rakheja, H. Wang, T. Palacios, I. Meric, K. Shepard, and D. Antoniadis, “A unified charge-current compact model for ambipolar operation in quasi-ballistic graphene transistors: Experimental verification and circuit-analysis demonstration,” IEEE Electron Devices Meeting (IEDM), Dec. 9-11, 2013.
  • S. Rakheja, V. Kumar and A. Naeemi, “Performance modeling for interconnects for conventional and emerging switches,” IEEE System Level Interconnect Prediction (SLIP) Workshop, June 02, 2013 (invited).
  • V. Kumar, S. Rakheja, and A. Naeemi, “Review of multi-layer graphene nanoribbons for on-chip interconnect applications,” International Symposium on Electromagnetic Compatibility (EMC), Aug. 5-9, 2013.
  • V. Kumar, S. Rakheja, and A. Naeemi, “Graphene nanoribbon interconnects,” Advanced Metallization Conference (ADMETA), Oct. 22-25, 2012.
  • S. Rakheja and A. Naeemi, “Compact modeling of spin-transport parameters in semiconducting channels in non-local spin-torque devices,” IEEE NANO, Aug. 20-23, 2012.
  • S. Rakheja and A. Naeemi, “Graphene nanoribbons for all-spin logic: effects of dimensional scaling on spin transport,” Semiconductor Research Corporation (SRC), TECHCON, Sep. 10-12, 2012 (won the best in session award).
  • S. Rakheja and V. Kumar, “Comparison of electrical, optical and plasmonic on-chip interconnects based on delay and energy considerations,” International Symposium on Quality Electronic Design (ISQED), March 18-20, 2012.
  • S. Rakheja and A. Naeemi, “Interconnect analysis in spin-torque devices: performance modeling, optimal repeater insertion, and circuit-size limits,” IEEE International Symposium on Quality Electronic Design (ISQED), March 18-20, 2012.
  • S. Rakheja and A. Naeemi, “On Physical limits and challenges of interconnects for spin devices,” IEEE NANO, Aug. 15-18, 2011.
  • S. Rakheja and A. Naeemi, “Interconnects for novel state variables: modeling physical limits and comparison with CMOS,” Semiconductor Research Corporation (SRC), TECHCON, Sep. 13-14, 2011.
  • V. Kumar, S. Rakheja and A. Naeemi, “Modeling and optimization of multi-layer graphene nanoribbon interconnects,” Semiconductor Research Corporation (SRC), TECHCON, Sep. 13-14, 2011.
  • S. Rakheja and A. Naeemi, “Performance, energy-per-bit, and circuit size limits of post-CMOS logic circuits- modeling, Analysis and comparison with CMOS logic,” IEEE International Interconnect Technology Conference (IITC), May, 2011 (invited).
  • V. Kumar, S. Rakheja, and A. Naeemi, “Modeling and optimization for multi-layer graphene nanoribbon conductors,” IEEE International Interconnect Technology Conference (IITC), May 9-12, 2011.
  • S. Rakheja and A. Naeemi, “Interconnection aspects of spin torque devices: delay, energy-per-bit, and circuit size modeling,” IEEE International Symposium on Quality Electronic Design (ISQED), March 14-16, 2011.
  • S. Rakheja, A. Naeemi and J.D. Meindl, “Performance and energy-per-bit modeling of interconnects for post-CMOS devices,” Semiconductor Research Corporation (SRC), TECHCON, Sep. 13-14, 2010.
  • S. Rakheja, A. Naeemi and J. D. Meindl, “Physical Limitations on delay and energy dissipation of interconnects for post-CMOS devices,” IEEE International Interconnect Technology Conference (IITC), June, 2010.
  • S. Kar, S. Rawat, S. Rakheja, and D. Reddy, “Extraction of parameters of high-K gate dielectrics from admittance data,” Proceedings of the SEMATECH Workshop on Electrical Characterization and Reliability for High-K Devices, 2004.

Software

  • Rakheja, S., Antoniadis, D. (2014). MVS Nanotransistor Model (Silicon). nanoHUB. doi:10.4231/D3H12V82S
  • Rakheja, S., Antoniadis, D. (2014). Ambipolar Virtual Source Compact Model for Graphene FETs. nanoHUB. doi:10.4231/D3MS3K273