Ramesh   Karri

Ramesh Karri

Professor, Electrical and Computer Engineering

Publications

http://eeweb.poly.edu/karri/Publications.html

Edited Books and Book Chapters

  1. R. Karri, J. Rajendran, and K. Rosenfeld, "Trojan Taxonomy" a book chapter in "Introduction to Hardware Security and Trust" edited by Mohammad Tehranipoor and Cliff Wang, Springer, New York, USA, 2011, pp.325-338.
  2. R. Karri and K. Rosenfeld, "Security and Testing" a book chapter in "Introduction to Hardware Security and Trust" edited by Mohammad Tehranipoor and Cliff Wang, Springer, New York, USA, 2011, pp.385-409.
  3. R. Karri and D. Goodman (EDITORS), "System-level power optimization for wireless multimedia communication" Kluwer Academic Publishers, ISBN: 1-4020-7204-X. This includes the following chapter co-authored with my student.
  4. R. Karri and P. Mishra, "Optimizing IPSec for energy-efficient secure wireless systems" a book chapter in "System-level power optimization for wireless multimedia communication" Kluwer Academic Publishers, 2002, pp. 133-152.

Patents

  1. US patent no. 8005209 "Invariance based concurrent error detection for the advanced encryption standard", August 2011.
  2. US patent no. 7212495 "Signalling for reserving a communications path", May 2007.
  3. US patent no. 6363506 "Method for self-testing integrated circuits", March 2002.
  4. US patent no. 6052808 "Maintenance registers with boundary scan interface", April 2000.

Journal Papers

  1. J. Rajendran, H. Zhang, C. Zhang, G.S. Rose, Y. Pino, O. Sinanoglu and R. Karri, Fault Analysis-based Logic Encryption, accepted in IEEE Transactions on Computers.
  2. X. Guo and R. Karri, "Recomputing with Permuted Operands - A Concurrent Error Detection Approach", accepted in IEEE Transactions on Computer-Aided Design.
  3. J. Rajendran, A. K. Kanuparthi, M. Zahran, S. Addepalli, G. Ormazabal, and R. Karri, "Securing processors against insider attacks: a circuit microarchitecture co-design approach", IEEE Design and Test Magazine, Vol. 30, Issue 2, pp. 35-44, 2013
  4. S. Kannan, J. Rajendran, O. Sinanoglu, and R. Karri, "Sneak Path Testing of Crossbar-based Resistive Random Access Memories," IEEE Transactions on Nanotechnology, vol.12, no.3, pp. 413-426, May 2013.
  5. G.S. Rose, H. Manem, J. Rajendran, R. Karri and R. Pino, "Leveraging Memristive Systems in the Construction of Digital Logic Circuits", Proceedings of the IEEE, Vol. 100, Issue 6, pp. 2033-2049, 2012.
  6. A. Kanuparthi, M. Zahran, and R. Karri, "Architecture Support for Dynamic Integrity Checking", IEEE Transactions on Information Forensics and Security, Vol. 7, Issue 1, pp. 321-332, 2012.
  7. J. Rajendran, H. Manem, R. Karri, and G.S. Rose, "An Energy-Efficient Memristive Threshold Logic Circuit", IEEE Transactions on Computers, Vol. 61, Issue 4, pp. 474-487, 2012.
  8. M. Tehranipoor, H. Salmani, X. Zhang, X. Wang, R. Karri, J. Rajendran and K. Rosenfeld, "Trustworthy Hardware: Trojan Detection Solutions and Design-for-Trust Challenges", IEEE Computer Magazine , Vol. 44, Issue 7, pp. 66-74, 2011.
  9. Yu Liu, Kaijie Wu, and Ramesh Karri, "Scan-based attacks on linear feedback shift register based stream ciphers", ACM Trans. Design Autom. Electr. Syst. 16(2): 20 2011
  10. Wenjing Rao, Chengmo Yang, Ramesh Karri, and Alex Orailoglu, "Toward Future Systems with Nanoscale Devices: Overcoming the Reliability Challenge", IEEE Computer Magazine, Vol. 44, Issue 2, pp. 46-53, 2011.
  11. R. Karri, J. Rajendran, K. Rosenfeld, and M. Tehranipoor" Trustworthy Hardware: Identifying and Classifying Hardware Trojans", IEEE Computer Magazine, Vol. 43, Issue 10, pp. 39-46, October 2010.
  12. K. Rosenfeld and R. Karri, "Attacks and defenses for JTAG," IEEE Design and Test of Computers., Vol. 27, No. 1, January 2010, pp. 35-47, Special Issue on Trustworthy Hardware.
  13. W. Rao, A. Orailoglu and R. Karri, "Logic Mapping in Crossbar-Based Nanoarchitectures", IEEE Design and Test of Computers, Vol. 26, No. 1, pp. 68-77, January 2009.
  14. K. Kim, K. Wu, and R. Karri, "The Robust QCA Adder Designs Using Composable QCA Building Blocks", IEEE Transactions on Computer-Aided Design, Vol. 26, No. 1, pp.176-183, January 2007.
  15. W. Rao, A. Orailoglu and R. Karri, "Towards Nanoelectronics Processor Architectures", Journal of Electronic Testing, Vol. 23, No. 2-3, pp. 235-25, Junee 2007.
  16. K. Kim, K. Wu and R. Karri, "Quantum-dot Cellular", Automata Design Guideline IEICE Transactions Special No. on fundamentals of electronics, communications and computer sciences, Vol. E89-A , No. 6, pp. 1607-1614, June 2006.
  17. N. Joshi, J. Sundararajan, K. Wu, B. Yang and R. Karri, "Tamper Proofing by Design Using Generalized Involution-Based Concurrent Error Detection for Involutional Substitution Permutation and Feistel Networks", IEEE Transactions on Computers, Vol. 55, No. 10, pp. 1230-1239, October 2006.
  18. B. Yang, R. Karri and D. A. Mcgrew, "A High-Speed Hardware Architecture for Universal Message Authentication Code", IEEE Journal on Selected Areas in Communications, Vol. 24, No. 10, pp. 1831-1839, October 2006.
  19. B. Yang, K. Wu and R. Karri, "Secure Scan: A Design-for-Test Architecture for Crypto Chips", IEEE Transactions on Computer-Aided Design, Vol. 25, No. 10, pp. 2287-2293, October 2006.
  20. N. Joshi, K. Wu, J. Sundarajan and R. Karri, "Concurrent error detection for involutional functions with applications in fault-tolerant cryptographic hardware design", IEEE Transactions on Computer-Aided Design, Vol. 25, No. 6, pp. 1163-1169, June 2006.
  21. K. Wu and R. Karri, "Algortihm-level recomputing with shifted operands: register transfer concurrent error detection technique", IEEE Transactions on Computer-Aided Design, Vol. 25, No. 3, pp. 413-422, March 2006.
  22. K. Kim, R. Karri and M. Potkonjak, "Micro-preemption synthesis: an enabling mechanism for multitask VLSI systems", IEEE Transactions on Computer-Aided Design, Vol. 25, No. 1, pp. 19-30, January 2006.
  23. B. Yang, R. Karri and D. A. Mcgrew, "Divide-and-concatenate: an architecture-level optimization technique for universal hash functions", IEEE Transactions on Computer-Aided Design, Vol. 24, No. 11, pp. 1740-1747, November 2005.
  24. H. Wang, M. Veeraraghavan, R.Karri and T. Li, "Design of a High-Performance RSVP-TE Hardware Signaling Accelerator", IEEE Journal on Selected Areas in Communications, Vol. 23, No. 8, pp. 1588-1595, August 2005.
  25. D. Sonecha, B. Yang, R. Karri, D. A. Mcgrew, "High-speed architectures for binary-tree based stream ciphers:Leviathan case study", Journal of Microprocessors and Microsystems, Vol. 28, Issue 10, pp. 573-584, December 2004.
  26. Kaijie Wu, Ramesh Karri, " Fault Secure Datapath Synthesis using Hybrid Time and Hardware Redundancy", IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, Vol 23, No. 10, pp 1476-1484, October, 2004.
  27. Kaijie Wu, Ramesh Karri, " Selectively Breaking Data Dependences to Improve the Utilization of Idle Cycles in Algorithm Level Re-Computing Data Paths", IEEE Transactions on Reliability, Vol 52 , No. 4, pp 501 - 511, December. 2003.
  28. Ramesh Karri, Piyush Mishra, "Optimizing the energy consumed by secure wireless sessions - Wireless Transport Layer Security case study", Journal of Mobile Networks and Applications (MONET), Kluwer Academic Publishers, Vol. 8, No. 2, pp. 177-185, April 2003.
  29. Kaijie Wu, Ramesh Karri, Piyush Mishra, "Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit RC6 Block Cipher", Special Issue on Defect and Fault Tolerance in VLSI Systems. Microelectronics Journal, Vol 34, No. 1, pp 31-39, January 2003.
  30. Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim, "Concurrent Error Detection Schemes for Fault Based Side-Channel Cryptanalysis of Symmetric Block Ciphers", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 21. No. 12, pp 1509-1517, December 2002.
  31. Ramesh Karri, Kaijie Wu, " Algorithm Level Re-Computing using Implementation Diversity: A Register Transfer Level Concurrent Error Detection Technique", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol 10. No. 6, pp 864 -875, December 2002.
  32. Kaijie Wu, R. Karri, " Algorithm Level Recomputing Using Allocation Diversity: A Register Transfer Level Approach To Time Redundancy Based Concurrent Error Detection", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 21. No. 9, pp 1077 -1087, September 2002.
  33. Ramesh Karri and B. Iyer, "Introspection: A Register Transfer Level Technique for Concurrent Error Detection and Diagnosis in Data Dominated Designs", ACM Transactions on Design Automation of Electronic Systems, vol.7, no.1, January 2002.
  34. M. Veeraraghavan, Ramesh Karri, T. Moors, M. Karol and R. Grobler, "Architectures and protocols that enable new applications on optical networks", IEEE Communications Magazine, vol. 39, no. 3, Mar 2001.
  35. Ramesh Karri, Kyosun Kim and M. Potkonjak, "Computer Aided Design of Fault Tolerant Application Specific Programmable Processors”, IEEE Transactions on Computers, vol 49, no 11, pp. 1272-1284, November 2000.
  36. I Hong, M. Potkonjak and Ramesh Karri, "Power optimization using Divide-and-Conquer for Minimization of the No. of Operations”, ACM Transactions on Design Automation of Electronic Systems, vol 6, no. 4, October 1999.
  37. N. Mukherjee, T. Chakraborty and Ramesh Karri, "Built-In Self Test: A Complete Test Solution for Communication Systems”, IEEE Communications Magazine, vol. 37, no. 6, pp. 72-78, June 1999.
  38. N. Mukherjee and Ramesh Karri, "An Integrated approach to On-Line/Off-Line BIST”, Journal of Electronic Testing and Testability Analysis, pp. 189-200, December 1998.
  39. A. Dasgupta and Ramesh Karri, "High-Reliability Low-Energy Microarchitecture Synthesis”, IEEE Transactions on CAD, vol. 17, no. 12, pp. 1273-1280, December 1998.
  40. Ramesh Karri, Karen Hogstedt and A. Orailoglu, "Computer Aided Design of Fault Tolerant VLSI Systems”, IEEE Design & Test of Computers, vol. 13, no.3, pp. 88-96, Fall 1996.
  41. Ramesh Karri and A. Orailoglu, "Time constrained scheduling during high level synthesis of Fault-Secure VLSI Digital Signal Processors”, IEEE Transactions on Reliability, vol. 45, no.3, pp. 404-412, September 1996.
  42. A. Orailoglu and Ramesh Karri, "Automatic Synthesis of Self-Recovering VLSI Systems”, IEEE Transactions on Computers, vol.45, no.2, pp. 131-142, February 1996.
  43. A. Dasgupta and Ramesh Karri, "Optimal Algorithms for Synthesis of Reliable Application Specific Heterogeneous Multiprocessors”, IEEE Transactions on Reliability, vol. 44, no. 4, pp. 603-613, December 1995.
  44. A. Orailoglu and Ramesh Karri, "Coactive Scheduling and Checkpoint Determination during High Level Synthesis of Self-Recovering Microarchitectures", IEEE Transactions on VLSI Systems, vol. 2, no. 3, pp. 304-311, September 1994.
  45. A. Orailoglu and Ramesh Karri, "Defect Tolerant Layout Synthesis”, International Journal of Electronics, pp. 1121-1133, June 1994.
  46. A. Orailoglu and Ramesh Karri, "Synthesis of Fault-Tolerant and Real Time Micro architectures”, Journal of Systems and Software, pp. 73-84, May 1994.
  47. Ramesh Karri and Alex Orailoglu, "Standard seven segment display for Burmese Numerals”, IEEE Transactions on Consumer Electronics, vol. 36, no. 4, pp. 959-961, November 1990.
  48. SHORT JOURNAL COMMUNICATIONS
  49. Miodrag Potkonjak, Ramesh Karri, Ingrid Verbauwhede, Kouichi Itoh, "Guest Editorial Integrated Circuit and System Security. IEEE Transactions on Information Forensics and Security," vol. 7, no. 1, pp. 1-2, 2012
  50. Ramesh Karri, "Guest editors introduction to special section on High Level Design Validation and Test”, IEEE Transactions on CAD, vol. 20, no. 2, March 2001.
  51. Ramesh Karri and M. Nicolaidis, "Online VLSI Testing - Guest Editors introduction”, IEEE Design and Test of Computers, vol 15, no. 4, pp 12-16, October-December 1998.

Conference Papers

  1. J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri, "Security Analysis of Integrated Circuit Camouflaging," in Proceedings of ACM Conference on Computer and Communications Security. (Best Student Paper Award)
  2. M. Rostami, F. Koushanfar, J. Rajendran, and R. Karri, "Hardware Security: Threat Models and Metrics," Proceedings of IEEE International Conference on Computer-Aided Design.
  3. J. Rajendran, O. Sinanoglu, and R. Karri, "VLSI Testing based Security Metric for IC Camouflaging," Proceedings of IEEE International Test Conference
  4. C. Liu, J. Rajendran, C. Yang and R. Karri, "Shielding Heterogeneous MPSoCs from Untrustworthy 3PIPs through Security-Driven Task Scheduling," Proceedings of IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. (Best Student Paper Award)
  5. H. Salmani, M. Tehranipoor, and R. Karri, "On design vulnerability analysis, hardware Trojan evaluation and Trust benchmarks developement," Proceedings of IEEE International Conference on Computer Design
  6. S. Kannan, O. Sinanoglu, and R. Karri, "Defects and fault modeling for Multi-level memristor-based memories," Proceedings of IEEE International Conference on Computer Design
  7. S.S. Ali, S.M. Said, O. Sinanoglu, and R. Karri, "Scan Attack in Presence of Mode-Reset Countermeasures," Proceedings of the International On-Line Testing Symposium
  8. J. Rajendran, H. Zhang, O. Sinanoglu, and R. Karri, "High-Level Synthesis for Security and Trust", Proceedings of the International On-Line Testing Symposium
  9. O. Sinanoglu, N. Karimi, J. Rajendran, R. Karri, Y. Jin, K. Huang, and Y. Makris, "Reconciling the IC Test and Security Dichotomy," Proceedings of the European Test Symposium, May 2013.
  10. J. Dubeuf, D. Hely, and R. Karri, "Run-time detection of hardware Trojans: The processor protection unit," Proceedings of the IEEE European Test Symposium, May 2013.
  11. X. Wang and R. Karri, "NumChecker: Detecting Kernel Control-flow Modifying Rootkits by Using Hardware Performance Counters," Proceedings of the IEEE/ACM Design Automation Conference, May 2013.
  12. X. Zhang, K. Xiao, M. Tehranipoor, J. Rajendran, and R. Karri, "A study on the effectiveness of Trojan detection techniques using a red team blue team approach", Proceedings of the IEEE VLSI Test Symposium, May 2013
  13. J. Rajendran, O. Sinanoglu, and R. Karri, "Is Split Manufacturing secure?", Proceedings of the IEEE/ACM Design Automation and Test Conference, pp. 1259-1264, Mar 2013
  14. G. Rose, J. Rajendran, N. McDonald, R. Karri, M. Potkonjak, and B. Wysocki, "Hardware Security Strategies Exploiting Nanoelectronic Circuits, Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 368-372, Jan 2013
  15. S. Kannan, J. Rajendran, O. Sinanoglu, and R. Karri, "Sneak Path Testing of Memristor-based Memories", Proceedings of the IEEE International Conference on VLSI Design, pp. 386-391, Jan 2013
  16. Jerry Backer and Ramesh Karri, "A High-Performance Low-Overhead Microarchitecture for Secure Program Execution", Proceedings of the IEEE International Conference on Computer Design, Oct 2012
  17. Arun K. Kanuparthi, Ramesh Karri, Gaston Ormazabal, and Sateesh Addepalli, "A High-Performance, Low-Overhead Microarchitecture for Secure Program Execution", Proceedings of the IEEE International Conference on Computer Design, Oct 2012
  18. S. Kannan, J. Rajendran, O. Sinanoglu, and R. Karri, "Engineering Crossbar based Emerging Memory Technologies", Proceedings of the IEEE International Conference on Computer Design, Oct 2012
  19. Arun K. Kanuparthi, Ramesh Karri, Gaston Ormazabal, and Sateesh Addepalli, "A Survey of Microarchitecture Support for Embedded Processor Security", Proceedings of the IEEE International Symposium on VLSI, Aug 2012.
  20. J. Rajendran, G. S. Rose, R. Karri, and M. Potkonjak, "Nano-PPUF: A Memristor-based security primitive", Proceedings of the IEEE International Symposium on VLSI, Aug 2012.
  21. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, "Security Analysis of Logic Obfuscation", Proceedings of the IEEE/ACM Design Automation Conference, pp. 83-89, June 2012, San Francisco, California.
  22. X. Guo and R. Karri, "Invariance-based concurrent error detection for advanced encryption standard", Proceedings of the IEEE/ACM Design Automation Conference, pp. 573-578, June 2012, San Francisco, California.
  23. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, "Logic Encryption: A Fault Analysis Perspective", Proceedings of the IEEE Design Automation and Test in Europe, pp. 953-958, March 2012, Dresden.
  24. J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, "Applying IC Testing Concepts to Secure ICs", Proceedings of the Government Microcircuit Applications and Critical Technology, March 2012, Las Vegas, Nevada.
  25. C. Malone, M. Zahran, and R. Karri, "Are hardware performance counters a cost effective way for integrity checking of programs?", Proceedings of ACM Workshop on Scalable Computing, pp. 71-76, October 2012, Chicago.
  26. J. Rajendran, V. Jyothi, and R. Karri, "Red team blue team approach to hardware trust assessment: The embedded systems challenge experience", Proceedings of the IEEE International Conference on Computer Design, pp. 285-288, October 2011, Amherst, Massachusetts.
  27. A. Durytskyy, M. Zahran, and R. Karri, "Improving Robustness of GPUs by Making Use of Faulty Parts", Proceedings of the IEEE International Conference on Computer Design, pp. 346-351, Amherst, Massachusetts, October 2011.
  28. J. Rajendran, R. Karri, and G. S. Rose, "Parallel Memristors: Improving Variation Tolerance in Memristive Digital Circuits”, Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2241 - 2244, May 2011, Rio de Janerio, Brazil.
  29. J. Rajendran, V. Jyothi, O. Sinanoglu, and R. Karri, "Design and Analysis of Ring Oscillator Based Design-for-Trust Technique”, Proceedings of the IEEE VLSI Test Symposium, pp. 105-110, May 2011, Anaheim, CA.
  30. K. Rosenfeld and R. Karri, "Security-Aware SoC Test Access Mechanisms”, Proceedings of the IEEE VLSI Test Symposiyum, pp. 100-104, May 2011, Anaheim, CA.
  31. J. Rajendran, H. Manem, R. Karri, and G.S. Rose, "An Approach to Tolerate Process Related Variations in Memristor-based Applications", IEEE International Symposium on VLSI Design, pp. 18-23, January 2011, Chennai, India.(Best Student Paper Award)
  32. A. K. Kanuparthi, M. Zahran, and R. Karri, "Feasibility Study of Dynamic Trusted Platform Module", Proceedings of the International Conference on Computer Design, pp. 350-355, October 2010, Amsterdam, Netherlands.
  33. J. Rajendran, H. Manem, R. Karri and G.S. Rose, "Memristor based Programmable Threshold Logic Array", Proceedings of IEEE Symposium on Nanoscale Architectures, June 2010, Anaheim, CA.
  34. J. Rajendran, H. Borad, S. Mantravadi and R. Karri, "SLICED: A Slide based Concurrent Error Detection Technique for Symmetric Block Ciphers", Proceedings of IEEE Symposium on Hardware Oriented Security and Trust, pp.112-117, June 2010, Anaheim, CA.
  35. K. Rosenfeld, E. Gavas and R. Karri, "Sensor Physcical Unclonable Functions", Proceedings of IEEE Symposium on Hardware Oriented Security and Trust, pp.112-117, June 2010, Anaheim, CA.
  36. J. Rajendran, J. Jimenez, E. Gavas, V. Padman and R. Karri, "A comprehensive taxonomy of hardware Trojans", Proceedings of IEEE Symposium on Circuits and Systems, May 2010, Paris, France.
  37. J. Li and R. Karri, "Optimized hardware architectures for Blake and Lake Hash functions", Proceedings of IEEE Symposium on Circuits and Systems, May 2010, Paris, France.
  38. K. Kim, Y. Oh, R. Karri and A. Orailoglu, "Leveraging CMOS design tools for QCA designs”, Proceedings of IEEE International SoC Desing Conference, pp. I183-I186, November 2008, Busan, South Korea.
  39. K. Kim and R. Karri, "Efficient construction of a minimal spanning tree avoiding rectilinear directional obstacles”, Proceedings of IEEE International SOC Design Conference, pp. I196-I199, November 2008, Busan, South Korea.
  40. R. Stern, N. Joshi, K. Wu and R. Karri, "Register Transfer Level Concurrent Error Detection in Elliptic Curve Crypto Implementations”, IEEE Workshop on Fault Diagnosis and Tolerance in Cryptography, pp. 112-119, August 2007, Vienna, Austria.
  41. W.Rao, A. Orailoglu adn R. Karri, "Logic Level Fault Tolerance Approaches Targeting Nanoelectronics PLAs", Proceedings of IEEE Design Automation and Test, pp.1-5, April 2007, Nice, France.
  42. Wenjing Rao, Alex Orailoglu, Ramesh Karri, "Fault Tolerant Nanoelectronic Processor Architectures”, Proceedings of the Asia and South Pacific Design Automation Conference, pp.311-316, January 2005, Shanghai, China.
  43. Tongquan Wei, Kaijie Wu, Ramesh Karri, Alex Orailoglu, "Fault Tolerant Quantum Cellular Array (QCA) Design using Triple Modular Redundancy with Shifted Operands”, Proceedings of Asia and South Pacific Design Automation Conference, Vol.2, pp.1192-1195, Jan 2005, Shanghai, China.
  44. Wenjing Rao, Alex Orailoglu, Ramesh Karri, "Fault Tolerant Arithmetic with Applications in Nanotechnology based System" Proceedings of International Test Conference, pp.1169-1173, 2004, Charlotte.
  45. Nikhil Joshi, Kaijie Wu, Ramesh Karri, "Concurrent Error Detection Schemes for Involution Ciphers”, Workshop on Cryptographic Hardware and Embedded Systems, pp.153-160, 2004, Boston.
  46. Kaijie Wu, Ramesh Karri, Grigori Kuznetsov, Michael Goessel, "Parity Based Concurrent Error Detection for the Advanced Encryption Standard", Proceedings of International Test Conference, pp.1509-1517, 2004, Charlotte.
  47. Bo Yang, Kaijie Wu, Ramesh Karri, "Scan-based Side-Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard", Proceedings of International Test Conference, pp.339-344, 2004, Charlotte.
  48. B. Yang, R. Karri, D. A. Mcgrew, "Divide-and-concatenate: an architecture level optimization technique for universal hash functions", Proceedings of IEEE/ACM Design Automation Conference (DAC), pp.1740-1747, June 2004, San Diego.
  49. Ramesh Karri, Piyush Mishra, "Investigation into the energy consumption characteristics of secure wireless session establishment and management”, Proceedings of IEEE Global Communications Conference, December 2003, San Francisco.
  50. Ramesh Karri, Piyush Mishra, "Analysis of energy consumed by secure session negotiation protocols in wireless networks”, International Workshop on Power and Timing Modeling, Optimization and Simulation, Springer-Verlag Lecture Notes in Computer Science, Integrated Circuit and System Design, pp.358-368, September 2003, Torino, Italy.
  51. Ramesh Karri and Piyush Mishra, "Design of energy efficient secure wireless networks using network simulators”, Proceedings of the IEEE International Conference on Communication, May 2003, Alaska.
  52. Ramesh Karri, Piyush Mishra, "Minimization of energy consumption of secure wireless session with QoS constraints”, Proceedings of the IEEE International Conference on Communication, Vol.4, pp. 2053-2057, April 2002, New York.
  53. Khary Alexander, Ramesh Karri, Igor Minkin, Kaijie Wu, Piyush Mishra, Xuan Li, " Towards 10-100 Gbps Cryptographic Architectures Proceedings of the International Symposium On Computer and Information Sciences, pp.25-30, 2002, Orlando.
  54. Kaijie Wu, Ramesh Karri, "Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis Proceedings of the International Test Conference, pp.1476-1485, 2003, Charlotte.
  55. Kaijie Wu, Ramesh Karri, "Exploiting idle cycles for algorithm level re-computing”, Proceedings of the Design Automation and Test in Europe, pp.842-846, 2002, Paris.
  56. Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim, " Fault-based side-channel cryptanalysis tolerant Rijndael symmetric block cipher architecture”, Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp.427-435, 2001, San Francisco.
  57. Kaijie Wu, Ramesh Karri, "Idle cycles based concurrent error detection of RC6 encryption”, Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp.200-205, 2001, San Francisco.
  58. Kaijie Wu, Ramesh Karri, "Algorithm Level Re-Computing - A Register Transfer Level Concurrent Error Detection Technique”, Proceedings of the International Conference on Computer Aided Design, pp.413-422, 2001, San Jose.
  59. Kaijie Wu, Ramesh Karri, "Algorithm Level Re-Computing with Allocation Diversity: A Register Transfer Level Time Redundancy Based Concurrent Error Detection Technique”, Proceedings of the International Test Conference, pp.1077-1087, 2001, Baltimore.
  60. Ramesh Karri, K. Wu, Y. Kim and P. Mishra, "Concurrent error detection schemes for side-channel fault analysis of 128-bit symmetric block ciphers", Proceedings of IEEE/ACM Design Automation Conference, pp.1509-1517, June 2001, Las Vegas, NV.
  61. J. Karrfalt, Ramesh Karri, Mark Brown, "Automatic Reconfiguration Tool”, Proceedings of Government Microelectronics Application Conference, March 2001, San Antonio, TX.
  62. K. Wu and Ramesh Karri, "Algorithmic Level Recomputing with Shifted Operands- A High Level Synthesis Approach to Concurrent Error Detection”, Proceedings of IEEE International Test Conference, pp.971-978, October 2000, Atlantic City, NJ.
  63. K. Wu and Ramesh Karri, "Algorithmic Level Recomputing with Shifted Operands- A High Level Synthesis Approach to Concurrent Error Detection”, Proceedings of NASA workshop on Military Applications of Programmable Designs and Technologies, pp.971-978, September 2000, Greenbelt, MD.
  64. R. Karri, K. Wu, Y. Kim and P. Mishra, "Concurrent error detection architectures for symmetric block ciphers”, Proceedings of NASA workshop on Military Applications of Programmable Designs and Technologies, pp.1509-1517, September 2000, Greenbelt, MD.
  65. R. Karri, K. Kim and M. Potkonjak, "Design Trade-offs during fault-tolerant data path synthesis", Proceedings of IEEE International Workshop on High Level Design Validation and Test, Vol.2, pp.1572-1575, November 1999 San Diego, CA.
  66. R. Karri N. Mukherjee and T. Chakrabarti, "Register Transfer Level approaches to on-line testing", Proceedings of IEEE International Workshop on On-Line Testing, July 1999, Rhodes, Greece.
  67. K. Kim, R. Karri and M. Potkonjak, " Synthesis of Fault-Tolerant Application Specific Programmable Processors", Proceedings of IEEE International Workshop on High Level Design Validation and Test, pp.1272-1284, November 1998, San Diego, CA.
  68. Ramesh Karri and N. Mukherjee, "VBIST: An Integrated approach to On-Line/Off-Line BIST”, Proceedings of IEEE International Test Conference, pp.910-917, October 1998, Washington DC.
  69. Ramesh Karri and N. Mukherjee, "An Integrated approach to On-Line/Off-Line BIST”, Proceedings of Lucent Conference on Electronic Testing, pp.910-917, April 1998, Princeton, NJ.
  70. Ramesh Karri, C. Stroud, and M. Ding, "Issues in Developing a Parametrized VHDL Library for On-Line Testing”, Proceedings of Lucent Conference on Electronic Testing, pp.479-488, April 1998, Princeton, NJ.
  71. Inki Hong, M. Potkonjak and Ramesh Karri, "Heterogeneous BISR-Approach Using System Level Synthesis Flexibility”, Proceedings of IEEE Asia and South Pacific Design Automation Conference, pp.289-294, February 1998.
  72. Kyosun Kim, Ramesh Karri and M. Potkonjak, "Micro-Preemption Synthesis: An Enabling Mechanism for Multi-Task VLSI Systems”, Proceedings of IEEE International Conference on CAD, pp.19-30, November 1997, San Jose, CA.
  73. Inki Hong, M. Potkonjak and Ramesh Karri, "Compilation and architecture techniques for power optimization of real-time DSP applications on programmable platforms”, Proceedings of IEEE International Conference on CAD, pp.108-113, November 1997, San Jose, CA.
  74. C. Stroud, M. Ding, S. Seshadri, I. Kim, S. Roy, S. Wu and R. Karri, "A Parametrized VHDL Library for On-Line Testing”, Proceedings of IEEE International Test Conference, pp.478-488, November 1997, Washington DC.
  75. Kyosun Kim, Ramesh Karri and M. Potkonjak, "Synthesis of Application Specific Programmable Processors”, Proceedings of IEEE/ACM Design Automation Conference, pp.353-358, June 1997, Sanfrancisco, CA.
  76. M. Potkonjak, Kyosun Kim and Ramesh Karri, "Synthesis and Selection of DCT Algorithms using Behavioral Synthesis-based Algorithm Space Exploration”, Proceedings of IEEE/ACM Design Automation Conference, pp.252-257, June 1997, Sanfrancisco, CA.
  77. Kyosun Kim, Ramesh Karri and M. Potkonjak, "Configurable Spare Processors: A new approach to system level fault-tolerance”, Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI, pp.295-303, November 1996, Boston, MA.
  78. Kyosun Kim, Ramesh Karri and M. Potkonjak, "Heterogeneous Built-In Resiliency of Application Specific Programmable Processors”, Proceedings of IEEE International Conference on CAD, pp.406-411, November 1996, San Jose, CA.
  79. Kyosun Kim, Ramesh Karri and M. Potkonjak, "Maximizing the Fault-Tolerance of Application Specific Signal Processors”, Proceedings of IEEE workshop on VLSI Signal Processing,pp. 283-292, October 1996, San francisco, CA.
  80. A Dasgupta and Ramesh Karri, "Hot-Electron Reliability Enhancement via Gate input Reordering”, Proceedings of IEEE/ACM Design Automation Conference, pp.819-824, June 1996, Las Vegas, NV.
  81. A Dasgupta and Ramesh Karri, "Electromigration Reliability Enhancement via Bus Activity Distribution”, Proceedings of IEEE/ACM Design Automation Conference, Las Vegas, NV, June 1996, pp.353-356.
  82. B. Iyer and Ramesh Karri, "Introspection: A zero overhead binding technique during self-diagnosing microarchitecture synthesis”, Proceedings of IEEE/ACM Design Automation Conference, pp.137-142, June 1996, Las Vegas, NV.
  83. A Dasgupta and Ramesh Karri, "RELSYN: A tool for synthesis of Reliable Application Specific Multiprocessor”, Proceedings of IEEE International Symposium on Circuits and Systems, Vol.4, pp.639-642, May 1996.
  84. B. Iyer, Ramesh Karri and I. Koren, "Phantom Redundancy: A High-Level Synthesis Technique for Manufacturability”, Proceedings of IEEE International Conference on CAD, pp.658-661, November 1995, San Jose, CA.
  85. A Dasgupta and Ramesh Karri, "Switch-Level Hot-Carrier Reliability Enhancement of VLSI Circuits”, Proceedings of IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems,pp. 63-71, November 1995, Lafayette, LA.
  86. A Dasgupta and Ramesh Karri, "Synthesis of Reliable Application Specific Heterogeneous Multiprocessor Systems”, Proceedings of IEEE International Symposium on Circuits and Systems, Vol.2, pp.1215-1218, May 1995, Seattle, WA.
  87. A Dasgupta and Ramesh Karri, "Simultaneous Scheduling and Binding for Power Minimization During Microarchitecture Synthesis”, Proceedings of IEEE International Symposium on Low Power Design, pp.1273-1280, April 1995, Dana point, CA.
  88. S. Sokolov and Ramesh Karri, "Allocation and Binding during Self Recovering Microarchitecture Synthesis”, Proceedings of IEEE International Conference on Computer Design, pp.327-330, October 1994, Cambridge, MA.
  89. Ramesh Karri and A. Orailoglu, "Area-Efficient Fault-Detection during Self-Recovering Microarchitectures Synthesis”, Proceedings of IEEE/ACM Design Automation Conference, pp.552-556, June 1994, San Diego, CA.
  90. Ramesh Karri, A. Orailoglu and K. Hogstedt, "Rapid Prototyping of Fault Tolerant VLSI Systems”, Proceedings of IEEE High Level Synthesis Workshop, pp.126-131, May 1994, Dana point, CA.
  91. A. Orailoglu and Ramesh Karri, "Simulated Annealing Based Yield Enhancement of Layouts”, Proceedings of IEEE Great Lakes VLSI Symposium, pp.166-169, March 1994, Notre Dame, IN.
  92. Ramesh Karri and A. Orailoglu, "A Framework For Synthesizing Fault-Tolerant Microarchitectures”, Proceedings of IEEE Custom Integrated Circuits Conference, pp. 5.6.1-5.6.4, May 1993, San Diego, CA.
  93. Ramesh Karri and A. Orailoglu, "Synthesis of Optimal Self-Recovering Microarchitectures”, Proceedings of IEEE International Symposium on Fault-Tolerant Computing, pp.286-289, June 1993, Tolouse, France.
  94. Ramesh Karri and A. Orailoglu, "High-Level Synthesis of Fault-Secure Microarchitectures”, Proceedings of IEEE/ACM Design Automation Conference, pp.429-433, June 1993, Dallas, CA.
  95. A. Orailoglu and Ramesh Karri, "A Design Methodology for the High-Level Synthesis of Fault-Tolerant ASICs”, Proceedings of IEEE Workshop on VLSI Signal Processing, pp.417-426, October 1992, Napa Valley, CA.
  96. Ramesh Karri and A. Orailoglu, "Transformation-Based Register Optimization in High-Level Synthesis”, Proceedings of IEEE Asilomar Conference on Circuits and Systems, Vol.2, pp.894-898, October 1992, Asilomar, CA.
  97. A. Orailoglu and Ramesh Karri, "High-Level Synthesis of Self-Recovering Microarchitectures”, Proceedings of IEEE International Conference on Computer Design, pp.286-289, October 1992, Cambridge, MA.
  98. Ramesh Karri and A Orailoglu, "Pipeline Data Path Synthesis of Fault-Tolerant Microarchitectures”, Proceedings of IEEE MidWest Symposium on Circuits and Systems, Vol. 2, pp.1572-1575, August 1992, Washington DC.
  99. Ramesh Karri and A. Orailoglu, "Scheduling with Rollback Constraints in High-Level Synthesis of Self-Recovering ASICs”, Proceedings of IEEE International Symposium on Fault-Tolerant Computing, pp.519-526, July 1992, Seattle, WA.
  100. Ramesh Karri and A. Orailoglu, "Transformation-Based Synthesis of Fault-Tolerant ASICs”, Proceedings of IEEE/ACM Design Automation Conference, pp.662-665, June 1992, Anaheim, CA.
  101. Ramesh Karri and A Orailoglu, "High-Level Synthesis of Fault-Tolerant ASICs”, Proceedings of IEEE International Symposium on Circuits and Systems, Vol. 1, pp.419-422, May 1992, San Diego, CA.
  102. Ramesh Karri and A Orailoglu, "ALPS: Algorithm for Pipelined data path synthesis Proceedings of IEEE International Symposium on Microarchitectures, pp.124-132, November 1991, Albuquerque, NM.
  103. Ramesh Karri, T. V. Gopal and P. R. K. Murti, "Boole - A Hardware Description Language”, Proceedings of the Second International Workshop on VLSI design, December 1988, Bangalore, India.
  104. Ramesh Karri, "Security imbedded authentication protocol”, Proceedings of the IEEE INFOCOM, pp.1105-1109, June 1988, Toronto, Canada.
  105. T.V. Gopal, Ramesh Karri and P. R. K. Murti, "CUWS - Central University Workstation for VLSI CAD”, Proceedings of Computer Society of India Annual Conference, January 1988, Madras, India.